Examples of the semiconductor devices (power semiconductor devices) having a breakdown voltage of 100 volts or higher that are used in power electronics include diodes, metal-oxide-semiconductor field-effect-transistors (MOSFETs), and insulated gate bipolar transistors (IGBTs). Those semiconductor devices are provided with the breakdown voltage structure for maintaining breakdown voltage resistance.
For example, the semiconductor device (vertical device) that flows current perpendicularly to the main surface of the semiconductor substrate has a termination structure formed so as to surround a region (active region) functioning as an active element, which serves as the breakdown voltage structure.
The semiconductor device (horizontal device) that flows current in parallel to the main surface of the semiconductor substrate has the breakdown voltage structure formed inside the active region.
The breakdown voltage structure functions to keep high voltage to be generated in the front surface of the main surface of the semiconductor substrate, irrespective of vertical devices or horizontal devices. High voltage is generated in the active region and the end of the semiconductor device in the vertical device, whereas high voltage is generated between electrodes inside the active region in the horizontal device.
Examples of the breakdown voltage of the semiconductor device include a reverse breakdown voltage of a diode and an off-breakdown voltage of a transistor. Such breakdown voltages are both defined as an upper-limit voltage to interrupt current (to flow no current).
While the semiconductor device interrupts current, a depletion layer extends inside the semiconductor substrate. This depletion layer can maintain high voltage. The application of a voltage exceeding the breakdown voltage leads to an avalanche breakdown in the portion inside the semiconductor substrate, in which an electric field is concentrated. As a result, the depletion layer is damaged, which causes short-circuit current to flow.
For example, in a PN junction diode (PIN diode) formed of a low-concentration N-type semiconductor substrate and a high-concentration P-type implantation layer, a depletion layer extends almost over the low-concentration N-type semiconductor substrate while the diode is turned off. Although it is this depletion layer that maintains high voltage, the breakdown voltage is limited due to an electric field concentration at the edge (peripheral edge) of the high-concentration P-type implantation layer.
The formation of a low-concentration P-type implantation layer in adjacent to the edge of the high-concentration P-type implantation layer causes the depletion layer to extend over both of the low-concentration N-type semiconductor substrate and the low-concentration P-type implantation layer. This relaxes the electric field at the edge of the high-concentration P-type implantation layer, increasing the breakdown voltage. This low-concentration P-type implantation layer is normally referred to as a reduced surface field (RESURF) layer or a junction termination extension (JTE). Such a breakdown voltage structure is referred to as a RESURF structure.
Although the depletion layer extends also in the RESURF layer in the RESURF structure, in terms of high breakdown voltage resistance, it is desirable to deplete the RESURF layer almost entirely up to the uppermost surface on a desired breakdown voltage. The condition for the above is defined by an amount of implantation (dose amount, implantation surface density) to the RESURF layer. If the amount of implantation to the entire RESURF layer is uniform, the optimum implantation amount is about 1×1012 cm−2 for silicon (Si) regardless of the concentration of the semiconductor substrate, and is 1×1013 cm−2 (with an activation rate of 100%) for polytype 4H silicon carbide (SiC). These are referred to as a RESURF condition.
The RESURF structure unfortunately has such a drawback that, in terms of high breakdown voltage resistance, an electric field is concentrated also on the peripheral edge of the RESURF layer. This limits the increasing of breakdown voltage to the avalanche breakdown on the peripheral edge of the RESURF layer. In other words, increasing breakdown voltage with the use of the normal RESURF structure is limited.
This problem can be avoided by gradually reducing the amount of implantation to the RESURF layer toward the outside, as described in Non-Patent Document 1 (or Patent Document 3 or 4). This structure divides the portion in which an electric field is concentrated into a plurality of portions, considerably reducing a maximum electric field inside the semiconductor.
The effects similar to those of Non-Patent Document 1 can be achieved also using the RESURF structure in which the amount of implantation to the RESURF layer is reduced stepwise toward the outside, as described in Patent Documents 1 and 2. In Patent Documents 1 and 2, an electric field is concentrated on the peripheral edge of the high-concentration P-type implantation layer, a boundary between the RESURF layers having different implantation amounts, and the outermost edge of the RESURF layer, and thus, the effect of relaxing an electric field is inferior to Non-Patent Document 1. Compared with the RESURF layer having a single implantation amount in its entirety, meanwhile, the portion in which an electric field is concentrated is divided, and thus, a maximum electric field inside the semiconductor substrate can be reduced.